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High-level circuit board design method

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High-level circuit board design method

The high-level printed board is a PCB circuit board formed by multiple layers of wiring layers and pp layers of insulating materials alternately pressed and bonded together by a laminator, and according to the design requirements, the conductive lines of each layer are mutually connected through vias and pads. even.

 

It has the characteristics of high assembly density, flexible design, more stable and reliable electrical relationship, etc., because electronic components are developing toward "small, light, thin, and short", driving the rapid development of multilayer circuit boards and becoming the highest output type of PCB products. The current multi-layer circuit board structure has become more complex, multi-variable, and high-rise. Therefore, the production of multi-layer printed boards requires PCB manufacturers to invest a lot of high-tech equipment and capital manpower.

 

The biggest difference between high-level pcb boards and single- and double-sided pcb boards: adding a VCC layer and a GND layer to the inner layer. The design method is basically similar. The key lies in how to optimize the inner layer wiring to achieve stronger electromagnetic compatibility.

 

The design of high-level pcb boards should be carried out from the following aspects:

1. Any PCB board needs to be assembled with other shells and other structures, so the general board shape is based on the overall structure of the product (from the perspective of convenient production, the shape should be as simple as possible to facilitate assembly and reduce production costs);

2. The number of layers should be considered based on circuit performance, circuit density, and the overall size of the circuit board;

3. The number of layers of the circuit board is preferably an even number. The asymmetric laminate structure will cause the board to warp and affect the soldering of SMD components.

 

Component placement should be considered from two aspects:

1. The arrangement should be dense and uniform, which is not only beautiful but also convenient for later assembly and maintenance;

2. According to the circuit principle, follow the circuit current trend, and reasonably decide the overall layout (if it is a high-frequency analog circuit, pay more attention to it). Prioritize the location of (central MCU chip, heterogeneous interference signal source), and then layout according to the schematic

 

Wiring requirements:

1. Under the premise of adjusting the wiring according to the circuit function, it is necessary to pay attention to less wiring on the surface of the component, to provide convenience for the later troubleshooting;

2. The signal lines that are thin, dense and easily interfered are placed on the inner layer;

3. Distribute copper foil evenly to avoid warping;

4. The board shape is more than 1.27mm away from the circuit to prevent the circuit from being damaged by the mechanical processing of the shape and cause short circuit between layers

 

Wire direction:

1. Separate the VCC, GND, and signal layers to reduce the interference between the three;

2. Avoid parallel lines between adjacent layers, reduce inter-layer coupling, and signal crosstalk;

3. The trace can be short but not long, small current signals are easily interfered;

4. The guide width is determined according to the impedance and current requirements of the circuit. Generally speaking, the VCC and GND lines are wider, and the signal lines are generally between 0.15mm and 0.25mm. Now there are many small calculation software programs such as:

 

It is recommended to use 0.5mm~2mm spacing for the power layer partition. The higher the voltage, the larger the spacing. The safety distance can be as wide as possible under the premise that the wiring can be arranged, reducing production costs and reducing product failures. In order to improve the anti-interference ability of the entire board, there are less wiring near the signal source, a reasonable grounding point, and a filter capacitor near the IC chip.

 

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Pub Time : 2020-10-22 16:33:55 >> News list
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